{"guid":"14281f92-873c-478c-a962-f1eb8b6c15d9","title":"SymbiFlow - Finally the GCC of FPGAs!","subtitle":"A fully FOSS, Verilog to bitstream, timing driven, cross FPGA, usable toolchain.","slug":"35c3-9631-symbiflow_-_finally_the_gcc_of_fpgas","link":"https://fahrplan.events.ccc.de/congress/2018/Fahrplan/events/9631.html","description":"The \u003ca href=\"http://symbiflow.github.io\"\u003eSymbiFlow project\u003c/a\u003e aims to be the \"GCC of FPGAs\" - a fully open source toolchain supporting, multiple FPGAs from different vendors. Allowing compilation from Verilog to bitstream without touching vendor provided tools, it includes support for large modern FPGAs like the Lattice ECP5 and Xilinx 7 series. These FPGAs can be used for things previously out of reach of FOSS tools, things like high resolution video and many gigabit networking. We have also documented the FPGA bitstreams to allow other new tools and a process for replicating this effort on new types of FPGAs!\n\n\u003cp\u003e\nThe \u003ca href=\"http://symbiflow.github.io\"\u003eSymbiFlow project\u003c/a\u003e aims to be the \"GCC of FPGAs\" - a fully open source toolchain supporting multiple FPGAs from multiple different vendors. FPGAs have been around since 1980s but most have previously require getting giant closed source proprietary black boxes from the FPGA vendor (10 gigabytes or more!). Thanks to SymbiFlow this is no longer the case! \n\u003c/p\u003e\u003cp\u003e\nLike the previous IceStorm efforts, SymbiFlow includes \u003cb\u003eboth\u003c/b\u003e documentation of FPGA bitstreams and a \u003cb\u003eworking\u003c/b\u003etoolchain for compiling Verilog into these bitstreams. Unlike previous efforts, this new toolchain supports industry standard timing driven place, and route and significantly larger designs. This makes SymbiFlow a \u003cb\u003ebig\u003c/b\u003e change over the previous Project IceStorm effort and enables support for large, modern FPGAs that can be used for things like high resolution video and many gigabit networking.\n\u003c/p\u003e\u003cp\u003e\nThis presentation will give you an update on the current status of the project. What currently works, the future roadmap and how you can help with the project and how to expand the number of supported FPGAs even further.\n\u003c/p\u003e\u003cp\u003e\nCurrently SymbiFlow is supporting the Lattice iCE40 plus two modern, capable and popular FPGAs architectures - the Lattice ECP5 and Xilinx 7 Series. The project has also gone to an effort to provide a well documented process for understanding FPGA bitstreams. This provides a clear pathway for new contributors to extend the tooling to support even more FPGAs!\n\u003c/p\u003e\u003cp\u003e\nCome find out about how a small group are changing the world of FPGA development!\n\u003c/p\u003e\n\n\u003ch3\u003eAbout FPGAs\u003c/h3\u003e\n\u003cp\u003e\nDue to their reconfigurable nature, FPGAs make hardware problems into software problems and enable anyone to building custom integrated circuits. This means you could create \u003cb\u003eyour\u003c/b\u003e ideal microcontroller, not what some manufacturer \u003cb\u003ethinks\u003c/b\u003e you want. You can have the \u003cb\u003eexact\u003c/b\u003e right set of peripherals including as many SPI, I2C or CAN as you want!\n\u003c/p\u003e\u003cp\u003e\nPreviously developing for FPGAs has require getting giant closed source proprietary black boxes from the FPGA vendor (10 gigabytes or more!). This has strongly hampered their adoption and reduced them to niche use cases. However, with the ending of Moore's law and things like \u003ca href=\"https://riscv.org/\"\u003eRISC-V\u003c/a\u003e, FPGAs have a strong role to play in enabling open source communities to participate in the explosion of new hardware design. They also enable us to apply the high speed of innovation and security we expect from an open source software.\n\u003c/p\u003e\n\n\u003ch3\u003ePresenters\u003c/h3\u003e\n\u003cp\u003e\n\u003ca href=\"https://blog.mithis.net\"\u003eTim 'mithro' Ansell\u003c/a\u003e is the founder of \u003ca href=\"http://code.timvideos.us\"\u003eTimVideos\u003c/a\u003e.He is known for having to many projects including hardware like the \u003ca href=\"https://hdmi2usb.tv\"\u003eHDMI2USB.tv\u003c/a\u003e, \u003ca href=\"https://tomu.im\"\u003eI'm Tomu\u003c/a\u003e and many more! Through this frustration with FPGA toolchains while developing these projects he ended up being heavily involved with the development of the \u003ca href=\"http://symbiflow.github.io\"\u003eSymbiFlow\u003c/a\u003e project.\n\u003c/p\u003e\n\n\u003ca href=\"https://symbiflow.github.io\"\u003ehttps://symbiflow.github.io\u003c/a\u003e\n\n\u003ca href=\"http://github.com/SymbiFlow\"\u003ehttp://github.com/SymbiFlow\u003c/a\u003e","original_language":"eng","persons":["Tim 'mithro' Ansell"],"tags":["35c3","9631","Hardware \u0026 Making"],"view_count":1284,"promoted":false,"date":"2018-12-28T00:00:00.000+01:00","release_date":"2018-12-28T01:00:00.000+01:00","updated_at":"2026-02-21T00:15:08.083+01:00","length":3723,"duration":3723,"thumb_url":"https://static.media.ccc.de/media/congress/2018/9631-hd.jpg","poster_url":"https://static.media.ccc.de/media/congress/2018/9631-hd_preview.jpg","timeline_url":"https://static.media.ccc.de/media/congress/2018/9631-hd.timeline.jpg","thumbnails_url":"https://static.media.ccc.de/media/congress/2018/9631-hd.thumbnails.vtt","frontend_link":"https://media.ccc.de/v/35c3-9631-symbiflow_-_finally_the_gcc_of_fpgas","url":"https://api.media.ccc.de/public/events/14281f92-873c-478c-a962-f1eb8b6c15d9","conference_title":"35C3: Refreshing Memories","conference_url":"https://api.media.ccc.de/public/conferences/35c3","related":[{"event_id":6382,"event_guid":"2912b643-f5a8-4bbd-8b24-74983bc55754","weight":32},{"event_id":6385,"event_guid":"9d8d4506-03b2-483d-aee5-d106f0a3eef5","weight":44},{"event_id":6404,"event_guid":"5b947f86-8ba1-4b99-adbe-7c5030deea0c","weight":38},{"event_id":6409,"event_guid":"a42e5a4f-fd9b-4571-bf17-483978afecb3","weight":44},{"event_id":6411,"event_guid":"42650545-4394-4455-a5f5-9efad111fedc","weight":46},{"event_id":6418,"event_guid":"dbd61e6a-dbde-4dcd-9b2e-73ba7ad62861","weight":43},{"event_id":6419,"event_guid":"96d10915-cc4b-42ca-ad75-15205db70d0b","weight":38},{"event_id":6422,"event_guid":"e8385c89-d33a-42d8-afb6-8ae28fe5c89d","weight":49},{"event_id":6430,"event_guid":"462f9320-3a0e-4785-82de-15343803c2ba","weight":41},{"event_id":6432,"event_guid":"de977841-8510-4172-9622-dd0563c2cb82","weight":43},{"event_id":6433,"event_guid":"30278963-3b07-49a8-96a7-2b24a8cf573b","weight":34},{"event_id":6434,"event_guid":"6beabddc-2dd6-43d2-9936-618d41d42cde","weight":29},{"event_id":6435,"event_guid":"9777cea0-ac06-4274-85db-908c1e87e2f4","weight":39},{"event_id":6442,"event_guid":"a24c67d2-9cad-41a5-ada4-eff706d29920","weight":191},{"event_id":6457,"event_guid":"74b9c748-970f-4693-ac7e-46fcc733d2b4","weight":33},{"event_id":6458,"event_guid":"3ff227f1-93cc-4a1d-8f0e-68fc12aea2c9","weight":40},{"event_id":6479,"event_guid":"8c84a37f-a8a5-4061-bfde-8da074ea8693","weight":34},{"event_id":6502,"event_guid":"e66cded3-7336-42bd-a7c8-d77073465ad2","weight":33}],"recordings":[{"size":null,"length":null,"mime_type":"application/x-subrip","language":"eng","filename":"DRAFT_35c3-9631-eng-deu-SymbiFlow_-_Finally_the_GCC_of_FPGAs.en_DRAFT.srt","state":"todo","folder":"","high_quality":true,"width":null,"height":null,"updated_at":"2024-02-18T19:13:08.678+01:00","recording_url":"https://cdn.media.ccc.de/congress/2018/DRAFT_35c3-9631-eng-deu-SymbiFlow_-_Finally_the_GCC_of_FPGAs.en_DRAFT.srt","url":"https://api.media.ccc.de/public/recordings/69748","event_url":"https://api.media.ccc.de/public/events/14281f92-873c-478c-a962-f1eb8b6c15d9","conference_url":"https://api.media.ccc.de/public/conferences/35c3"},{"size":381,"length":3723,"mime_type":"video/mp4","language":"eng","filename":"35c3-9631-eng-SymbiFlow_-_Finally_the_GCC_of_FPGAs.mp4","state":"new","folder":"h264-hd","high_quality":true,"width":1920,"height":1080,"updated_at":"2018-12-28T17:50:59.894+01:00","recording_url":"https://cdn.media.ccc.de/congress/2018/h264-hd/35c3-9631-eng-SymbiFlow_-_Finally_the_GCC_of_FPGAs.mp4","url":"https://api.media.ccc.de/public/recordings/31313","event_url":"https://api.media.ccc.de/public/events/14281f92-873c-478c-a962-f1eb8b6c15d9","conference_url":"https://api.media.ccc.de/public/conferences/35c3"},{"size":382,"length":3723,"mime_type":"video/mp4","language":"deu","filename":"35c3-9631-deu-SymbiFlow_-_Finally_the_GCC_of_FPGAs.mp4","state":"new","folder":"h264-hd","high_quality":true,"width":1920,"height":1080,"updated_at":"2018-12-28T17:51:15.780+01:00","recording_url":"https://cdn.media.ccc.de/congress/2018/h264-hd/35c3-9631-deu-SymbiFlow_-_Finally_the_GCC_of_FPGAs.mp4","url":"https://api.media.ccc.de/public/recordings/31314","event_url":"https://api.media.ccc.de/public/events/14281f92-873c-478c-a962-f1eb8b6c15d9","conference_url":"https://api.media.ccc.de/public/conferences/35c3"},{"size":512,"length":3723,"mime_type":"video/mp4","language":"eng-deu","filename":"35c3-9631-eng-deu-SymbiFlow_-_Finally_the_GCC_of_FPGAs_hd.mp4","state":"new","folder":"h264-hd","high_quality":true,"width":1920,"height":1080,"updated_at":"2018-12-28T17:51:30.574+01:00","recording_url":"https://cdn.media.ccc.de/congress/2018/h264-hd/35c3-9631-eng-deu-SymbiFlow_-_Finally_the_GCC_of_FPGAs_hd.mp4","url":"https://api.media.ccc.de/public/recordings/31315","event_url":"https://api.media.ccc.de/public/events/14281f92-873c-478c-a962-f1eb8b6c15d9","conference_url":"https://api.media.ccc.de/public/conferences/35c3"},{"size":191,"length":3723,"mime_type":"video/mp4","language":"eng-deu","filename":"35c3-9631-eng-deu-SymbiFlow_-_Finally_the_GCC_of_FPGAs_hd-slides.mp4","state":"new","folder":"slides-h264-hd","high_quality":true,"width":1920,"height":1080,"updated_at":"2018-12-28T18:15:11.592+01:00","recording_url":"https://cdn.media.ccc.de/congress/2018/slides-h264-hd/35c3-9631-eng-deu-SymbiFlow_-_Finally_the_GCC_of_FPGAs_hd-slides.mp4","url":"https://api.media.ccc.de/public/recordings/31328","event_url":"https://api.media.ccc.de/public/events/14281f92-873c-478c-a962-f1eb8b6c15d9","conference_url":"https://api.media.ccc.de/public/conferences/35c3"},{"size":207,"length":3723,"mime_type":"video/mp4","language":"eng-deu","filename":"35c3-9631-eng-deu-SymbiFlow_-_Finally_the_GCC_of_FPGAs_sd.mp4","state":"new","folder":"h264-sd","high_quality":false,"width":720,"height":576,"updated_at":"2018-12-28T18:15:43.834+01:00","recording_url":"https://cdn.media.ccc.de/congress/2018/h264-sd/35c3-9631-eng-deu-SymbiFlow_-_Finally_the_GCC_of_FPGAs_sd.mp4","url":"https://api.media.ccc.de/public/recordings/31329","event_url":"https://api.media.ccc.de/public/events/14281f92-873c-478c-a962-f1eb8b6c15d9","conference_url":"https://api.media.ccc.de/public/conferences/35c3"},{"size":39,"length":3723,"mime_type":"audio/opus","language":"eng","filename":"35c3-9631-eng-SymbiFlow_-_Finally_the_GCC_of_FPGAs_opus.opus","state":"new","folder":"opus","high_quality":false,"width":0,"height":0,"updated_at":"2018-12-28T18:22:24.380+01:00","recording_url":"https://cdn.media.ccc.de/congress/2018/opus/35c3-9631-eng-SymbiFlow_-_Finally_the_GCC_of_FPGAs_opus.opus","url":"https://api.media.ccc.de/public/recordings/31344","event_url":"https://api.media.ccc.de/public/events/14281f92-873c-478c-a962-f1eb8b6c15d9","conference_url":"https://api.media.ccc.de/public/conferences/35c3"},{"size":56,"length":3723,"mime_type":"audio/mpeg","language":"eng","filename":"35c3-9631-eng-SymbiFlow_-_Finally_the_GCC_of_FPGAs_mp3.mp3","state":"new","folder":"mp3","high_quality":false,"width":0,"height":0,"updated_at":"2018-12-28T18:23:36.628+01:00","recording_url":"https://cdn.media.ccc.de/congress/2018/mp3/35c3-9631-eng-SymbiFlow_-_Finally_the_GCC_of_FPGAs_mp3.mp3","url":"https://api.media.ccc.de/public/recordings/31347","event_url":"https://api.media.ccc.de/public/events/14281f92-873c-478c-a962-f1eb8b6c15d9","conference_url":"https://api.media.ccc.de/public/conferences/35c3"},{"size":358,"length":3723,"mime_type":"video/webm","language":"eng-deu","filename":"35c3-9631-eng-deu-SymbiFlow_-_Finally_the_GCC_of_FPGAs_webm-sd.webm","state":"new","folder":"webm-sd","high_quality":false,"width":720,"height":576,"updated_at":"2018-12-28T18:26:43.485+01:00","recording_url":"https://cdn.media.ccc.de/congress/2018/webm-sd/35c3-9631-eng-deu-SymbiFlow_-_Finally_the_GCC_of_FPGAs_webm-sd.webm","url":"https://api.media.ccc.de/public/recordings/31353","event_url":"https://api.media.ccc.de/public/events/14281f92-873c-478c-a962-f1eb8b6c15d9","conference_url":"https://api.media.ccc.de/public/conferences/35c3"},{"size":780,"length":3723,"mime_type":"video/webm","language":"eng-deu","filename":"35c3-9631-eng-deu-SymbiFlow_-_Finally_the_GCC_of_FPGAs_webm-hd.webm","state":"new","folder":"webm-hd","high_quality":true,"width":1920,"height":1080,"updated_at":"2018-12-28T20:27:00.535+01:00","recording_url":"https://cdn.media.ccc.de/congress/2018/webm-hd/35c3-9631-eng-deu-SymbiFlow_-_Finally_the_GCC_of_FPGAs_webm-hd.webm","url":"https://api.media.ccc.de/public/recordings/31415","event_url":"https://api.media.ccc.de/public/events/14281f92-873c-478c-a962-f1eb8b6c15d9","conference_url":"https://api.media.ccc.de/public/conferences/35c3"}]}