{"guid":"374a5739-4b48-2020-2020-202020202020","title":"Verilog Design Patttern","subtitle":null,"slug":"7JW9KH","link":"https://c3voc.de","description":"In the last time, Verilog becomes quite popular among Hackers - based on the hype the FOSS Yosys Toolchain kicked off for the iCE40 FPGAs.\n\nIt is a known fact, that everybody can learn faster from someone which already did the stuff more than once. While freelancing in Chip Design for two decades I like to share Design Pattern in Verilog.\n\nDesign Pattern means,\n- styleguides which results in readable code,\n- how to write good and fast Finite State Machines, why they are so useful,\n- how to deal with clock-domain crossing and why we might need that,\n- how to structure your source code design files,\n- how to use Makefiles for that,\nand much, much more.\nAll with code snippets to show and explain.\n\nI can't be stopped, until the time slot is closed.","original_language":"deu","persons":["hsank"],"tags":["eh18","52"],"view_count":217,"promoted":false,"date":"2018-04-01T00:00:00.000+02:00","release_date":"2018-04-01T02:00:00.000+02:00","updated_at":"2026-04-08T19:30:05.871+02:00","length":4464,"duration":4464,"thumb_url":"https://static.media.ccc.de/media/conferences/eh2018/52-hd.jpg","poster_url":"https://static.media.ccc.de/media/conferences/eh2018/52-hd_preview.jpg","timeline_url":"https://static.media.ccc.de/media/conferences/eh2018/374a5739-4b48-2020-2020-202020202020-timeline.jpg","thumbnails_url":"https://static.media.ccc.de/media/conferences/eh2018/374a5739-4b48-2020-2020-202020202020-thumbnails.vtt","frontend_link":"https://media.ccc.de/v/7JW9KH","url":"https://api.media.ccc.de/public/events/374a5739-4b48-2020-2020-202020202020","conference_title":"Easterhegg 2018","conference_url":"https://api.media.ccc.de/public/conferences/eh18","related":[{"event_id":2757,"event_guid":"303801f5-9eaf-41a9-9022-92dc5cd702d2","weight":1},{"event_id":5220,"event_guid":"57533942-4659-2020-2020-202020202020","weight":10},{"event_id":5222,"event_guid":"42464643-3358-2020-2020-202020202020","weight":13},{"event_id":5225,"event_guid":"57423939-4845-2020-2020-202020202020","weight":14},{"event_id":5229,"event_guid":"53464646-4151-2020-2020-202020202020","weight":11},{"event_id":5233,"event_guid":"4a433356-4456-2020-2020-202020202020","weight":18},{"event_id":5235,"event_guid":"52535255-5245-2020-2020-202020202020","weight":10},{"event_id":5236,"event_guid":"585a5337-4554-2020-2020-202020202020","weight":11},{"event_id":5240,"event_guid":"39474e46-4733-2020-2020-202020202020","weight":18},{"event_id":5241,"event_guid":"43335341-4154-2020-2020-202020202020","weight":15},{"event_id":5244,"event_guid":"4a473753-5039-2020-2020-202020202020","weight":15},{"event_id":5246,"event_guid":"33515633-5950-2020-2020-202020202020","weight":12}],"recordings":[{"size":874,"length":4464,"mime_type":"video/mp4","language":"deu","filename":"eh18-52-deu-Verilog_Design_Patttern_hd.mp4","state":"new","folder":"h264-hd","high_quality":true,"width":1920,"height":1080,"updated_at":"2018-04-01T22:53:49.495+02:00","recording_url":"https://cdn.media.ccc.de/events/eh2018/h264-hd/eh18-52-deu-Verilog_Design_Patttern_hd.mp4","url":"https://api.media.ccc.de/public/recordings/24304","event_url":"https://api.media.ccc.de/public/events/374a5739-4b48-2020-2020-202020202020","conference_url":"https://api.media.ccc.de/public/conferences/eh18"},{"size":209,"length":4464,"mime_type":"video/mp4","language":"deu","filename":"eh18-52-deu-Verilog_Design_Patttern_sd.mp4","state":"new","folder":"h264-sd","high_quality":false,"width":720,"height":576,"updated_at":"2018-04-01T23:15:13.581+02:00","recording_url":"https://cdn.media.ccc.de/events/eh2018/h264-sd/eh18-52-deu-Verilog_Design_Patttern_sd.mp4","url":"https://api.media.ccc.de/public/recordings/24305","event_url":"https://api.media.ccc.de/public/events/374a5739-4b48-2020-2020-202020202020","conference_url":"https://api.media.ccc.de/public/conferences/eh18"},{"size":67,"length":4452,"mime_type":"audio/mpeg","language":"deu","filename":"eh18-52-deu-Verilog_Design_Patttern_mp3.mp3","state":"new","folder":"mp3","high_quality":false,"width":0,"height":0,"updated_at":"2018-04-01T23:19:07.336+02:00","recording_url":"https://cdn.media.ccc.de/events/eh2018/mp3/eh18-52-deu-Verilog_Design_Patttern_mp3.mp3","url":"https://api.media.ccc.de/public/recordings/24306","event_url":"https://api.media.ccc.de/public/events/374a5739-4b48-2020-2020-202020202020","conference_url":"https://api.media.ccc.de/public/conferences/eh18"},{"size":42,"length":4452,"mime_type":"audio/opus","language":"deu","filename":"eh18-52-deu-Verilog_Design_Patttern_opus.opus","state":"new","folder":"opus","high_quality":false,"width":0,"height":0,"updated_at":"2018-04-01T23:19:39.583+02:00","recording_url":"https://cdn.media.ccc.de/events/eh2018/opus/eh18-52-deu-Verilog_Design_Patttern_opus.opus","url":"https://api.media.ccc.de/public/recordings/24307","event_url":"https://api.media.ccc.de/public/events/374a5739-4b48-2020-2020-202020202020","conference_url":"https://api.media.ccc.de/public/conferences/eh18"},{"size":318,"length":4464,"mime_type":"video/webm","language":"deu","filename":"eh18-52-deu-Verilog_Design_Patttern_webm-sd.webm","state":"new","folder":"webm-sd","high_quality":false,"width":720,"height":576,"updated_at":"2018-04-01T23:20:19.468+02:00","recording_url":"https://cdn.media.ccc.de/events/eh2018/webm-sd/eh18-52-deu-Verilog_Design_Patttern_webm-sd.webm","url":"https://api.media.ccc.de/public/recordings/24308","event_url":"https://api.media.ccc.de/public/events/374a5739-4b48-2020-2020-202020202020","conference_url":"https://api.media.ccc.de/public/conferences/eh18"},{"size":1142,"length":4464,"mime_type":"video/webm","language":"deu","filename":"eh18-52-deu-Verilog_Design_Patttern_webm-hd.webm","state":"new","folder":"webm-hd","high_quality":true,"width":1920,"height":1080,"updated_at":"2018-04-02T00:30:05.964+02:00","recording_url":"https://cdn.media.ccc.de/events/eh2018/webm-hd/eh18-52-deu-Verilog_Design_Patttern_webm-hd.webm","url":"https://api.media.ccc.de/public/recordings/24309","event_url":"https://api.media.ccc.de/public/events/374a5739-4b48-2020-2020-202020202020","conference_url":"https://api.media.ccc.de/public/conferences/eh18"}]}