{"guid":"84493789-7cab-4057-b7c7-0d7f5075668d","title":"Verilog Synthesis and more with Yosys","subtitle":null,"slug":"eh16-40-verilog_synthesis_and_more_with_yosys","link":"https://fahrplan.eh16.easterhegg.eu/events/40.html","description":"At 32C3 I presented a free and open source verilog to bitstream flow for iCE40 FPGAs. This flow consists of Yosys (Verilog Synthesis), Arachne-pnr (Place and Route), and Project IceStorm (Low-level tools and FPGA reverse engineering).\n\nThis talk has a wider focus and discusses various applications of Yosys, i.e.:\n\nSynthesis:\n- ASIC Synthesis\n- FPGA Synthesis for iCE40 FPGAs (complete flow)\n- FPGA Synthesis for Xilinx 7-Series FPGAs\n- Synthesis to simple Verilog or BLIF files\n\nFormal Verification:\n- Property checking with build-in SAT solver\n- Property checking with ABC using miter circuits\n- Property checking with yosys-smtbmc and SMT solvers\n- Formal and/or structural equivalence checking\n\nI also briefly discuss Open Source tools for related topics, such as Verilog simulation and SAT/SMT solving.","original_language":"deu","persons":["Clifford Wolf"],"tags":["Science \u0026 Engineering"],"view_count":570,"promoted":false,"date":"2016-03-25T18:00:00.000+01:00","release_date":"2016-03-27T01:00:00.000+01:00","updated_at":"2026-01-29T15:00:10.775+01:00","length":6796,"duration":6796,"thumb_url":"https://static.media.ccc.de/media/conferences/eh2016/40-sd.jpg","poster_url":"https://static.media.ccc.de/media/conferences/eh2016/40-sd_preview.jpg","timeline_url":"https://static.media.ccc.de/media/conferences/eh2016/84493789-7cab-4057-b7c7-0d7f5075668d-timeline.jpg","thumbnails_url":"https://static.media.ccc.de/media/conferences/eh2016/84493789-7cab-4057-b7c7-0d7f5075668d-thumbnails.vtt","frontend_link":"https://media.ccc.de/v/eh16-40-verilog_synthesis_and_more_with_yosys","url":"https://api.media.ccc.de/public/events/84493789-7cab-4057-b7c7-0d7f5075668d","conference_title":"Easterhegg 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