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The nextpnr FOSS FPGA place-and-route tool
46 min

The nextpnr FOSS FPGA place-and-route tool

the next step forward in open source FPGA tools

35C3: Refreshing Memories
End-to-end formal ISA verification of RISC-V processors with riscv-formal
29 min

End-to-end formal ISA verification of RISC-V processors with riscv-formal

34C3: TUWAT
Verilog Synthesis and more with Yosys
113 min

Verilog Synthesis and more with Yosys

Easterhegg 2016